1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit technologies, and more particularly to wiring line structures for integrated circuits and methods of forming the same.
2. Description of the Related Art
Conventionally, semiconductor device operating voltages have been reduced to one volt and lower over time. Moreover, power consumption has increased due to higher circuit density and device leakage currents making resistive losses in the substrate important for power delivery to the die. Traditional electrical wiring for substrates and circuit boards used with electronic devices typically involves a single via diameter on a layer. To supplement the power in specific areas of a die high current capacity conductors are desired. At the same time, for some dielectric media such as alumina, impedance matching and shielding for GHz operational frequencies also requires small diameter vias to provide 50 ohms impedance.
U.S. Pat. No. 6,265,308 issued to Bronner et al., the complete disclosure of which, in its entirety, is herein incorporated by reference, teaches a process of forming wiring in a semiconductor interlayer dielectric. As Bronner teaches, generally, the resistance of metal lines is defined by a feature's height, width and resistivity. The height is often limited by arrays of the smallest feature size (e.g., memory arrays). However, due to capacitance and space minimization in these areas, the height of the metal lines may be limited. Conversely, using lines with a large line width results in an increased chip size. Therefore, the resistance of metal lines is globally restricted to values which do not allow for high current densities due to Joule heating of highly, resistive lines.
As a result, power bus lines, which are designed to carry high current densities, and signal or equipotential lines that do not allow a large potential gradient along the line, are typically designed on an additional metal level using a thicker metal height, or using broad or parallel lines on thin metal levels, which again, tend to increase the chip size. Thus, if thicker metal lines are desired for increased current capacity (and thus higher bus speeds for example), then the conventional techniques for producing thick metal lines generally include increasing the thickness of the metal layer and increasing the number of metal layers, each of which increases chip size and the number of processing steps, thereby resulting in increased manufacturing time and costs.
Additionally, for a given combination of conducting and insulating materials, the most desirable way to significantly reduce the capacitance of metal lines with narrow spacing is to make the metal stack sufficiently thin. Similarly, low resistance lines are produced by increasing their thickness accordingly. However, conventionally, both characteristics cannot be sufficiently united on one metal level. Moreover, conventional designs with single via diameters on each layer tend to compromise both impedance and power requirements. Likewise, similar constraints are encountered in the circuit definition and fabrication for substrates, circuit boards, and other interconnect devices which can be used with integrated circuit devices. Therefore, there remains a need for wiring conduits through the substrate of an integrated circuit that can be designed to satisfy both impedance and power requirements.